![]() The solution, since 2011 or so, has been to use the third dimension. In a recent presentation, TSMC Deputy Director Jin Cai suggested that, based on simulation results, planar transistors are limited to a minimum gate length of about 25nm. ![]() Manufacturers need to continue to reduce contact pitch to shrink the total silicon area, while reducing the gate length at a more moderate rate. Overly aggressive gate length scaling makes device performance worse, not better. Interface scattering reduces carrier mobility in very small devices, while drain-induced barrier lowering (DIBL) and other short channel effects blur the difference between the “on” and “off” states. Since the end of Dennard scaling, though, performance metrics have become more complicated as devices have behaved less and less like ideal transistors. For most of the industry’s history, shorter gate lengths meant faster devices because the carriers didn’t have to travel as far. The gate length, on the other hand, helps define the device performance. For a given process technology, the required silicon area determines the manufacturing cost of the device. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors can fit in a given space. The gate, plus a dielectric spacer, fits between the source and drain contacts. How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts?įor planar transistors, the two values are approximately the same.
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